A vast majority of digital electronic circuits include synchronous sequential logic circuits that require a clock signal for their operations. One or more clock signals are distributed to every part of the circuit containing such synchronous sequential logic circuits. For large circuits, it is a general practice to organize the clock distribution as a hierarchical arrangement in the form of a “clock tree” that distributes the clock over the entire circuit.
The power consumption of an electronic circuit is largely dependant on the switching of the logic circuits in response to the clock signal because the static power consumption, especially for CMOS circuits that are widely used in electronic devices, is extremely low. The predominant dynamic power consumption is the result of charging and discharging of internal and external capacitors. Increased power dissipation also results in reduced reliability as the circuit components operate at a higher temperature. The increased power dissipation may also require the use of expensive packaging and/or heat dissipation arrangements to manage the heat generated, thereby resulting in increased cost.
In several applications or under certain conditions in a given application, some synchronous, sequential-logic circuits are not in use. This condition may arise frequently in programmable devices such as Field Programmable Gate Arrays (FPGAs) depending on the program used. Current circuit arrangements supply the clock signal to all points whether or not the synchronous, sequential logic at those points is in use. For example, the clock signal in a clock tree is supplied to all branches and leaves regardless or whether a particular leaf or branch is in use or not. This scheme results in wasted power. In the case of FPGAs, this inefficiency can result in limitations on gate density and/or maximum clock speed. The consumption of power can be reduced by selectively enabling only the clock to only those leaves or branches of the clock tree that are connected to active sequential circuits.
U.S. Pat. Nos. 5,652,529 and 5,703,498 disclose a method for selective enabling of a clock tree by selectively switching of the clock in column and sector arrangements. However, these inventions merely provide a selection mechanism, leaving the actual selection of branch and leaf to the programmer. This results in a process that is relatively complex and inefficient to control the clock tree.